Flash memory device is a non-volatile memory device capable of maintaining information stored in its memory cell without a power supply. One advantage of the flash memory device is its capacity for block-by-block memory erasure, and another advantage is its low electric consumption. The flash memory device can be classified into a stacked-gate cell, a split-gate cell, and the like, according to their corresponding cell transistor gate structures. A split-gate cell which includes a control gate physically implemented laterally adjacent to a floating gate is characterized by excellent efficiency in its erasure and program functionality. This high efficiency effectively protects the split-gate cell from inadvertent over-erasure of stored data.
As known in split-gate flash technology, forward-tunneling voltage (FTV) and reverse-tunneling voltage (RTV) are highly correlated to the floating gate profile. Also, RTV is correlated to a tiny nitride spacer formed between the lower edges of the floating gate and the control gate. This nitride spacer, also called a reverse-tunneling nitride (RTN) spacer, is used to prevent write disturbance caused by reverse tunneling. Thus, how to control the profile of the floating gate and maintain the film thickness of the RTN spacer are important issues for improving program and erasure performance. In one case of fabricating a floating gate with a tapered profile, a sharp tip at the corner edge of the floating gate is obtained to achieve desired low FTV. However, this tapered profile usually accompanies a thin RTN spacer since it is difficult to control the process of etching a nitride spacer on the slanted sidewall, causing unwanted low RTV. Comparatively, in another case of fabricating a floating gate with a vertical profile, a thicker RTN spacer is obtained to achieve desired high RTV, but the later etching process always rounds the corner edge of the floating gate to get unwanted high FTV for lack of the sharp poly-tip.
Accordingly, when the conventional floating gate having the tapered profile or the vertical profile is employed with the known nitride spacer etching process, a trade-off between FTV and RTV will be inevitably entailed. It is therefore desirable to provide a novel profile of the floating gate for maintaining low FTV and high RTV simultaneously.